q_b (sub_wire3) // synopsys translate_off. Code: module altram(Ain,clk,ROM_A_out) input Ain input clk output ROM_A_out wire rom_01 wire rom_02 wire rom_03 wire rom_04 wire rom_05 wire rom_06 Dual_Rom inst_01(.address_a(Ain).address_b(rom_01).clock(clk).q_a(rom_01).q_b(rom_02)) Dual_Rom inst_02(.address_a(rom_02).address_b(rom_03).clock(clk).q_a(rom_03).q_b(rom_04)) Dual_Rom inst_03(.address_a(rom_04).address_b(rom_05).clock(clk).q_a(rom_05).q_b(rom_06)) Dual_Rom inst_04(.address_a(rom_06).address_b(rom_07).clock(clk).q_a(rom_07).q_b(ROM_A_out)) endmodule module Dual_Rom ( address_a, address_b, clock, q_a, q_b) input address_a input address_b input clock output q_a output q_b wire sub_wire0 = 8'h0 wire sub_wire1 = 1'h0 wire sub_wire2 wire sub_wire3 wire q_a = sub_wire2 wire q_b = sub_wire3 altsyncram altsyncram_component (.
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